The present invention relates to a planar laminate substrate base and method of fabricating printed circuit boards (PCBs) and related semiconductor devices starting from this substrate, that offers at least a 2:1 reduction in the physical dimensions of current technology PCBs and related semiconductor devices.
With the advent of higher processing speeds and as the reduction in electronic component geometries accelerates, manufactures of laminate substrates are being pushed to provide base materials and components that are capable of delivering performance values that exceed current material capabilities and production techniques. Because of rapidly emerging technologies, the boundaries between semiconductor packaging, and PCB technologies are blurred; these must all be considered concurrently in an overarching approach in order to optimize the substrate design. In the semiconductor industry, assembly and packaging is a critical competitive factor of the semiconductor product as it affects operating frequency, power, reliability, and cost.
The future base material and components will need to possess better electrical characteristics such as lower Er (Dk); lower Loss Tangents (Df); highly electrically conductive metallurgy to minimize resistive voltage drops and to effectively deliver power to the chip; low-inductance connections to reduce simultaneous switching noise; low-dielectric constant insulator materials to better match board impedances and to reduce undesirable parasitic capacitances; and advanced thermal interface materials to manage high power densities on the chip and to improve the ability to work in higher temperature environments.
Most importantly is that these base materials will need to lend themselves to production techniques that allow for feature sizes in the line width (traces) and line spacing (trace spacing) down to 10μ (0.00039 inch) or less and a dielectric (substrate) thickness of 25μ (0.00098 inch) or less. The key to resolving these problems and accomplishing a further miniaturization of electronic components lies in achieving an extremely thin, yet resilient copper layer on a dielectric substrate base, that has a high peel strength. Such a planar laminate substrate would possess a low etch factor in the etching phases of fabrication and result in much finer traces and trace spacings.
A conventional printed circuit board (PCB) consists of a fully resin cured fiberglass-reinforced epoxy dielectric substrate base clad on at least one side with a layer of copper. Currently, there are three mainstream industry standard methods of adhering the copper to the base: electroless/electrophoretic deposition; foil buildup (laminated foil on uncured laminate); and RCC (resin coated copper). Each of these methods utilize a dendretic structure for the adhesion of the copper to the substrate base.
In the first method, the substrate is prepared by roughing up the bonding surface and or applying a bonding agent that is cured onto the substrate prior to the deposition of the copper. The deposition of copper must be thick enough to achieve a dendritic adhesion to the substrate surface so as to maintain a high peel strength of the copper layer. Generally this requires a copper layer that is 0.00007 inch (7 mils) thick. It is this thickness that governs the limits of line width (traces) and spacing. This product can't accommodate traces and spacing less than 20μ (0.0008 inch) wide each because it is limited by the physical characteristics of the dendritic structures required to achieve the adequate peel strength characteristic.
The second method affixes copper foil to a uncured dielectric substrate by heat and pressure in a lamination press. Again, product made by this method can't accommodate traces and spacing less than 20μ (0.0008 inch) wide each because it is limited by the physical characteristics of the dendritic structures required to achieve the adequate peel strength characteristic as well as the etch factor effect on the copper in the related etching process steps.
The third method affixes thin copper foil to the surface of the substrate through the use of an adhesive (usually this is the same resin that the substrate laminar base is made of with the exception that it is uncured resin). Here the deep dendritic structure is formed on the copper foil before it is coated with the adhesive. It also requires a copper layer that is 0.0007 inches thick. This product can't accommodate traces and trace spacing less than 25μ (0.00098 inch) wide because of the physical characteristics of the dendritic structures as well as the etch factor effect on the copper in the related etching process steps.
The present invention affixes the copper via vapor deposition after the wetting angle has been decreased on a non-fiberglass reinforced polymer substrate surface by irradiating the ion particles on the surface and blowing a reactive gas thereon under vacuum conditions. This method for increasing the adhesion of the copper onto a polymer substrate is well known in the art and discussed in U.S. Pat. No. 5,783,641 “Processes for Modifying Surfaces of Polymers, and Polymer Having Surfaces Modified by Such.” This increases the adhesive strength of the polymer surface such that vapor deposition of copper need only yield a diminished thickness of 0.02 mil (0.00002 inch or 0.5μ) to reach a peel strength sufficient to ensure the adherence of the copper to the substrate base. This product, when utilized with the fabrication methods discussed herein, can accommodate line width (traces) and spacing less than 10 microns wide. With these closer tolerances between traces, the fabrications thereof will have tighter spacings and the likely hood of Cathodic Anodic Filament growth between adjacent penetrations through the substrate, along fiberglass reinforcement strands, that cause short circuits on the PCB would be enhanced. Thus the need for the use of non-fiberglass reinforced polymer substrate boards is necessary with the present invention.
Henceforth, an order of magnitude reduction of the size of the planar laminate substrate used to fabricate organic laminate substrate PCBs and semiconductor components coupled with a complex series of laser drilling, copper buildup, resist coating, etching, resist strip, and lamination steps, that yield a 2:1 or better reduction in physical size, would fulfill a long felt need in the electronics industry. The introduction of an adhesive layer affixed to the substrate further allows for greater flexibility in multiple configuration design and fabrication. This new invention utilizes and combines known and new technologies in a unique and novel configuration to overcome the aforementioned problems and accomplish this.